1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display (LCD) device having an improved aperture ratio and no wavy noise and a method of fabricating the same through a four mask process.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices use the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. The liquid crystal molecules have long, thin, shapes, and have an alignment direction. The alignment direction can be controlled by applying an electric field to influence the alignment of the liquid crystal molecules. Due to an optical anisotropy property of liquid crystal, the refraction of incident light depends on the alignment direction of the liquid crystal molecules. Thus, by properly controlling the applied electric field, an image having a desired brightness can be produced.
The LCD device includes an upper substrate having a common electrode, a lower substrate having a pixel electrode and a liquid crystal layer interposed between the upper and lower substrates. The upper and lower substrates are referred to as color filter and array substrates, respectively. The molecules of the liquid crystal layer are driven by a vertical electric field induced between the common electrode and the pixel electrode.
Among the known types of LCD devices, active matrix LCD (AM-LCD) devices, which have thin film transistors (TFTs) and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superior ability in displaying moving images.
FIG. 1 is a perspective view showing an LCD device according to the related art. In FIG. 1, the LCD device 51 includes a first substrate 5, a second substrate 10 and a liquid crystal layer (not shown) between the first and second substrates 5 and 10. The first and second substrates 5 and 10 are facing and spaced apart from each other. A black matrix 6 and a color filter layer including red (R), green (G) and blue (B) color filters 7a, 7b and 7c are formed on an inner surface of the first substrate 5 and a common electrode 9 is formed on the color filter layer.
A gate line 14 and a data line 26 are formed on the second substrate 10. The gate line 14 and the data line 26 cross each other to define a pixel region P. A thin film transistor (TFT) T is connected to the gate line 14 and the data line 26. A pixel electrode 32 connected to the TFT T is formed in the pixel region P. The pixel electrode 32 is formed of a transparent conductive material, such as indium-tin-oxide (ITO).
The second substrate, which is referred to as an array substrate, of the LCD device may be fabricated through a five mask process or a six mask process. For example, a five mask process for an array substrate may include a first mask process of forming a gate electrode and a gate line (and a gate pad); a second mask process of forming an active layer and an ohmic contact layer over the gate electrode; a third mask process of forming a data line (and a data pad), a source electrode and a drain electrode; a fourth mask process of forming a passivation layer having a contact hole exposing the drain electrode; and a fifth mask process of forming a pixel electrode connected to the drain electrode through the contact hole. Since the array substrate is fabricated through a complicated mask process, a possibility of deterioration increases and a production yield decreases. In addition, since fabrication time and cost increase, a competitiveness of product is weakened.
To solve the above problems, a four mask process has been suggested. FIG. 2 is a plan view showing an array substrate for an LCD device fabricated through a four mask process according to the related art. In FIG. 2, a gate line 62 and a data line 98 cross each other on a substrate 60 to define a pixel region P. A gate pad 66 is formed at one end of the gate line 62, and a data pad 99 is formed at one end of the data line 98. A gate pad terminal GP is formed on the gate pad 66, and a data pad terminal DP is disposed on the data pad 99.
A thin film transistor (TFT) T including a gate electrode 64, a first semiconductor layer 91, a source electrode 94 and a drain electrode 96 is disposed near a crossing portion of the gate and data lines 62 and 98. The gate electrode 64 is connected to the gate line 62 and the source electrode 94 is connected to the data line 98. The source and drain electrodes 94 and 96 are spaced apart from each other on the first semiconductor layer 91. A pixel electrode PXL is formed in the pixel region P and contacts the drain electrode 96.
A metal layer 97 having an island shape and contacting the pixel electrode PXL overlaps a portion of the gate line 62. The portion of the gate line 62 as a first capacitor electrode, the metal layer 97 as a second capacitor electrode and a gate insulating layer (not shown) between the first and second capacitor electrodes as a dielectric material constitute a storage capacitor Cst.
A second semiconductor layer 92 is formed under the data line 98, and a third semiconductor layer 93 is formed under the metal layer 97. Since the second semiconductor layer 92 extends from the first semiconductor layer 91, a portion of an active layer of the first semiconductor layer 91 is not covered by the gate electrode 64 and is exposed to light from a backlight unit (not shown) under the substrate 60. Since the first semiconductor layer 91 is formed of amorphous silicon, a photo leakage current is generated in the first semiconductor layer 91 due to the light from the backlight unit. As a result, electrical characteristics of the TFT T are degraded due to the photo leakage current.
The second semiconductor layer 92 protrudes beyond the data line 98 because a photoresist (PR) pattern for the second semiconductor layer 92 has a greater width than another PR pattern for the data line 98. The protruding portion of the second semiconductor layer 92 is exposed to the light from the backlight unit or an ambient light. Since the second semiconductor layer 92 is formed of amorphous silicon, a light leakage current is generated in the second semiconductor layer 92. The light leakage current causes a coupling of signals in the data line 98 and the pixel electrode PXL generate electrical defects, such as a wavy noise, when displaying images. A black matrix (not shown) covers the protruding portion of the second semiconductor layer 92 so as to reduce the aperture ratio of the LCD device. Because the pixel electrode PXL is connected to the drain electrode 96 through a contact hole, the first semiconductor layer 91 can be exposed to an ambient light. Thus, the black matrix also covers the contact hole, which further reduces the aperture ratio of the LCD device.
FIGS. 3A and 3B are cross-sectional views taken along lines IIIa-IIIa′ and IIIb-IIIb′ of FIG. 2, respectively. As shown in FIGS. 3A and 3B, the first semiconductor layer 91 is formed under the source and drain electrodes 94 and 96 and the second semiconductor layer 92 is formed under the data line 98 in an array substrate fabricated through a four mask process according to the related art. The second semiconductor layer 92 extends toward the first semiconductor layer 91. The first semiconductor layer 91 includes an intrinsic amorphous silicon layer as an active layer 91a and an impurity-doped amorphous silicon layer as an ohmic contact layer 91b. The second semiconductor layer 92 includes an intrinsic amorphous silicon layer 92a and an impurity-doped amorphous silicon layer 92b. 
A portion of the active layer 91a can not be completely covered by the gate electrode 64. The portion of the active layer 91a is exposed to light from the backlight unit (not shown), and thus a photo current is generated in the active layer 91a. This photo current becomes a leakage current in the TFT T of the pixel region P. As a result, electrical characteristics of the TFT T are degraded.
The intrinsic amorphous silicon layer 92a of the second semiconductor layer 92 protrudes beyond the data line 98. When the protruding portion of the intrinsic amorphous silicon layer 92a is exposed to light from the backlight unit or an ambient light, it is repeatedly activated and inactivated, and thus a light leakage current is generated. Since the light leakage current is coupled with the signal in the pixel electrode PXL, the directional alignment of the liquid crystal molecules is abnormally distorted. Accordingly, undesired wave-shaped thin lines are displayed on the LCD device.
A distance between the data line 98 and the pixel electrode PXL is generally about 4.75 μm in consideration of alignment error in an LCD device formed through a five mask process or a six mask process. The intrinsic amorphous silicon layer 92a of the second semiconductor layer 92 protrudes beyond the data line 98 by about 1.7 μm in an LCD device formed through a four mask process. Accordingly, a distance D between the data line 98 and the pixel electrode PXL is about 6.45 μm (=4.75 um+1.7 um) due to the protrusion of the intrinsic amorphous silicon layer 70. As a result, the pixel electrode PXL in the LCD device formed through the four mask process is farther away from the data line 98 than in the LCD device formed through the five mask process or the six mask process, and a width WI of a black matrix BM to shield the data line 98 and the distance D increases in the LCD device through the four mask process. The increase in the width of the black matrix BM reduces aperture ratio.
FIGS. 4A to 4G are cross-sectional views along line IIIa-IIIa′ of FIG. 2, FIGS. 5A to 5G are cross-sectional views along line V-V′ of FIG. 2, and FIGS. 6A to 6G are cross-sectional views taken along VI-VI′ of FIG. 2, showing a process of fabricating an array substrate for an LCD device through a four mask process according to the related art.
FIGS. 4A, 5A and 6A show a first mask process. In FIGS. 4A, 5A and 6A, a gate line 62, a gate pad 66 and a gate electrode 64 are formed on a substrate 60 having a pixel region P, a switching region S, a gate pad region GP, a data pad region D and a storage region C through a first mask process. The gate pad 66 is formed at one end of the gate line 62.
FIGS. 4B to 4E, 5B to 5E and 6B to 6E show a second mask process. In FIGS. 4B, 5B and 6B, a gate insulating layer 68, an intrinsic amorphous silicon layer 70, an impurity-doped amorphous silicon layer 72 and a metallic material layer 74 are formed on the substrate 60 having the gate line 62. A photoresist (PR) layer 76 is formed on the metallic material layer 74. A mask M is disposed over the photoresist layer 76. The mask M has a transmitting portion B1, a blocking portion B2 and a half-transmitting portion B3. The transmitting portion B1 has a relatively high transmittance so that light through the transmitting portion B1 can completely change the PR layer 76 chemically. The blocking portion B2 shields light completely. The half-transmitting portion B3 has a slit structure or a half-transmitting film so that intensity or transmittance of light through the half-transmitting portion B3 can be lowered. As a result, a transmittance of the half-transmitting portion B3 is smaller than that of the transmitting portion B1 and is greater than that of the blocking portion B2.
The half-transmitting portion B3 and the blocking portions B2 at both sides of the half-transmitting portion B3 correspond to the switching region S. The transmitting portion B1 corresponds to the gate pad region GP, and the blocking portion B2 corresponds to the storage region C and the data pad region DP. The PR layer 76 is exposed to light through the mask M.
In FIGS. 4C, 5C and 6C, first to third PR patterns 78a to 78c are formed in the switching region S, the data pad region DP and the storage region C, respectively. The metallic material layer 74, the impurity-doped amorphous silicon layer 72 and the intrinsic amorphous silicon layer 70 are etched using the first to third PR patterns 78a to 78c. 
In FIGS. 4D, 5D and 6D, first to third metal patterns 80, 82 and 86 are formed under the first to third PR patterns 78a to 78c, and first to third semiconductor layers 90a to 90c are formed under the first to third metal patterns 80, 82 and 86. The second metal pattern 82 extends from the first metal pattern 80, and the third metal pattern 86 having an island shape is formed in the storage region C. The first to third semiconductor layers 90a to 90c include an intrinsic amorphous silicon pattern 70a and an impurity-doped amorphous silicon pattern 72a. 
A thinner portion of the first PR pattern 78a is removed to expose the first metal pattern 80 by an ashing process. At the same time, boundary portions of the first to third PR patterns 78a to 78c are also removed. As a result, the first to third PR patterns 78a to 78c are partially removed to form fourth to sixth PR patterns 79a to 79c exposing the first to third metal patterns 80, 82 and 86, respectively. The first to third metal patterns 80, 82 and 86 and the impurity-doped amorphous silicon layer 72a of the first to third semiconductor layers 90a to 90c are etched using the fourth to sixth PR patterns 79a to 79c. 
In FIGS. 4E, 5E and 6E, the first metal pattern 80 (of FIG. 4D) in the switching region S is etched to form source and drain electrodes 94 and 96, the second metal pattern 84 (of FIG. 6E) in the data pad region DP is etched to form a data line 98 and a data pad 99, and the third metal pattern 86 (of FIG. 4D) in the storage region C is etched to form a metal layer 97. The intrinsic amorphous silicon layer 70a (of FIG. 4D) and the impurity-doped amorphous silicon layer 72a (of FIG. 4D) of the first semiconductor pattern 90a (of FIG. 4D) are etched to form an active layer 91a and an ohmic contact layer 91b, respectively, of a first semiconductor layer 91. The active layer 91a is exposed through the ohmic contact layer 91b and is over-etched so that impurities do not remain on the active layer 92a. In addition, the second and third semiconductor patterns 90b and 90c (of FIGS. 6D and 4D) are etched to form second and third semiconductor layers 92 and 93, respectively. An overlapped portion of the gate line 62 as a first capacitor electrode and the metal layer 97 as a second capacitor electrode constitutes a storage capacitor Cst with the interposed gate insulating layer 68 and the third semiconductor layer 93.
FIGS. 4F, 5F, and 6F show a third mask process. In FIGS. 4F, 5F, and 6F, a passivation layer PAS is formed on the substrate 60 having the data line 98. The passivation layer PAS is patterned through a third mask process to form a drain contact hole CH1 exposing the drain electrode 96, a storage contact hole CH2 exposing the metal layer 97, and a data pad contact hole CH4 exposing the data pad 99. Also, the passivation layer PAS and the gate insulating layer 68 are patterned through the third mask process to form a gate pad contact hole CH3 exposing the gate pad 66.
FIGS. 4G, 5G and 6G show a four mask process. In FIGS. 4G, 5G and 6G, a transparent conductive material is deposited on the passivation layer PAS and patterned through a fourth mask process to form a pixel electrode PXL, a gate pad terminal GPT and a data pad terminal DPT. The pixel electrode PXL contacts the drain electrode 96 through the drain contact hole CH1 and the metal layer 97 through the storage contact hole CH2. The gate pad terminal GPT contacts the gate pad 66 through the gate pad contact hole CH3, and the data pad terminal DPT contacts the data pad 99 through the data pad contact hole CH4.
Through the above four mask process, the array substrate is fabricated. As explained above, the intrinsic amorphous silicon layer of the second semiconductor layer protrudes beyond the data line. Accordingly, wavy noise occurs and aperture ratio is reduced. Further, since the active layer is connected to the intrinsic amorphous silicon layer of the second semiconductor layer, a portion of the active layer is not covered by the gate electrode. Accordingly, the light leakage current is generated in the thin film transistor. Also, because the active layer should be formed thickly in consideration of the over-etching, fabrication time and product cost increase. Moreover, since the pixel electrode is connected to the drain electrode through a contact hole and the first semiconductor layer is exposed to an ambient light, a black matrix covering the contact hole is required. As a result, aperture ratio is further reduced due to the black matrix.